• Keynote 4

 Integrated Magnetic Probe and Application for Device Diagnosis

Kunihiro Asada

VLSI Design and Education Center (VDEC), University of Tokyo, Japan

Email: asada@silicon.t.u-tokyo.ac.jp

Abstract

The spatial resolution of coil-based magnetic probe is determined by the coil size. A smaller coil has a higher spatial resolution but a weaker level of output signal, which results in a worse signal-to-noise (S/N) ratio. A solution of this trade-off problem is integration of a small coil with a low-noise amplifier on a semiconductor chip. In this presentation, firstly, structures and fabrication procedure of our integrated magnetic probes will be introduced along with their characteristics. Next, an estimation method of current distribution from measurement data of the magnetic probe is introduced, as a theoretical basis of the integrated magnetic probe application. It is a reverse modeling from magnetic field data to current distribution in circuit. Though it is a straightforward procedure to calculate magnetic field based on a known current distribution in general, a practical problem is the existence of noise. Here a method to estimate most-likely current distribution from magnetic field with random noise will be introduced under the constraint of KCL. Finally, two examples of application will be shown. The first example is measurement results of gate leak current in power devices (IGBT), where the location of the leakage has been successfully detected based on “valley detection method” with a good agreement of a microscopic device diagnosis. The second example is an analysis of power network integrity of LSI. By comparing a normal chip with an abnormal chip with missing VIAs in power network, the magnetic probe has successfully detected subtle differences in magnetic fields, which has been translated to an abnormal power current map analytically. Both the above examples show that the integrated magnetic probe has a potential to be utilized for improving device reliability and fabrication technologies.

Biography

Dr. Kunihiro Asada is Emeritus Professor of the University of Tokyo, Japan. He received the BS, MS and PhD from the University of Tokyo in 1975, 1977 and 1980, respectively. In 1980 he joined the Faculty of Engineering, the University of Tokyo. From 1985 to 1986 he stayed at Edinburgh University as a visiting scholar. From 1990 to 1992 he served as the editor of IEICE Transactions on Electronics. In 1996 he established VLSI Design and Education Center (VDEC) in the University of Tokyo and served as the Director of VDEC from 2000 to 2018. He also served as the Chair of IEEE/SSCS Japan Chapter in 2001 -2002 and the Chair of IEEE Japan Chapter Operation Committee in 2007-2008. He is currently a managing director of the Takeda Foundation and the Chair of the Young Takeda Award Committee. His research interest is design and analysis of integrated systems and devices. He is a member of IEEE, IEICE and IEEJ.